EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 57

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
August 2005
Notes to
(1)
(2)
(3)
(4)
EP1SGX10C
EP1SGX10D
EP1SGX25C
EP1SGX25D
EP1SGX25F
EP1SGX40D
EP1SGX40G
Table 3–3. Stratix GX Source-Synchronous Differential I/O Resources
Device
This is the number of receiver or transmitter channels in the source-synchronous (I/O bank 1 and 2) interface of
the device.
Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mbps.
One of the two fast PLLs in EP1SGX10C and EP1SGX10D devices supports DPA.
Two of the four fast PLLs in EP1SGX40D and EP1SGX40G devices support DPA
Table
3–3:
Fast PLLs
2
2
4
4
2
2
2
(3)
(3)
(4)
(4)
have four dedicated fast PLLs for clock multiplication.
the maximum number of channels in each Stratix GX device that support
DPA.
The receiver and transmitter channels are interleaved so that each I/O
row in I/O banks 1 and 2 of the device has one receiver channel and one
transmitter channel per row.
channels with DPA layout in EP1SGX10, EP1SGX25, and EP1SGX40
devices. In EP1SGX10 devices, only fast PLL 2 supports DPA operations.
Pin Count
1,020
1,020
1,020
1,020
672
672
672
672
Channels
Receiver
(1)
22
22
39
39
39
39
45
45
Transmitter
Figures 3–6
Channels
(1)
22
22
39
39
39
39
45
45
Source-Synchronous Signaling With DPA
Stratix GX Device Handbook, Volume 1
and
Channel Speed
Transmitter
Receiver &
(Gbps)
3–7
1
1
1
show the fast PLL and
1
1
1
1
1
(2)
Table 3–3
10,570
10,570
25,660
25,660
25,660
25,660
41,250
41,250
LEs
shows
3–7