EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 35

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Table 2–8. Code Conversion
XGMII RXC
0
1
1
1
1
1
1
1
1
00 through FF
07
07
9C
FB
FD
FE
FE
See IEEE 802.3 reserved code
groups
XGMII RXD
Receiver State Machine
The receiver state machine operates in GIGE and XAUI modes. In GIGE
mode, the receiver state machine replaces invalid code groups with
9’h1FE. In XAUI mode, the receiver state machine translates the XAUI
PCS code group to the XAUI XGMII code group.
code conversion. The conversion adheres to the IEEE 802.3ae
specification.
Byte Deserializer
The byte deserializer takes a single width word (8 or 10 bits) from the
transceiver logic and converts it into double-width words (16 or 20 bits)
to the phase compensation FIFO buffer. The byte deserializer is bypassed
when single width mode (8 or 10 bits) is used at the PLD interface.
Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer resides in the transceiver
block at the programmable logic device (PLD) boundary. This buffer
compensates for the phase difference between the recovered clock within
the transceiver and the recovered clock after it has transferred to the PLD
core. The phase compensation FIFO buffer is four words deep and cannot
be bypassed.
Dxx.y
K28.0 or K28.3 or K28.5
K28.5
K28.4
K27.7
K29.7
K30.7
Invalid code group
See IEEE 802.3 reserved
code groups
PCS code-group
Stratix GX Device Handbook, Volume 1
Normal Data
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Invalid XGMII character
Reserved code groups
Table 2–8
Stratix GX Transceivers
Description
shows the
2–25