EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 15

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Transmitter Path
This section describes the data path through the Stratix GX transmitter
(see
following modules:
■
■
■
■
■
■
Transmitter PLL
Each transceiver block has one transmitter PLL, which receives the
reference clock and generates the following signals:
■
■
■
The INCLK clock is the input into the transmitter PLL. There is one INCLK
clock per transceiver block. This clock can be fed by either the REFCLKB
pin, PLD routing, or the inter-transceiver routing line. See the section
“Stratix GX Clocking” on page 2–30
transceiver lines.
The transmitter PLL in each transceiver block clocks the circuits in the
transmit path. The transmitter PLL is also used to train the receiver PLL.
If no transmit channels are used in the transceiver block, the transmitter
PLL can be turned off.
PLL.
Figure
Transmitter PLL
Transmitter phase compensation FIFO buffer
Byte serializer
8B/10B encoder
Serializer (parallel to serial converter)
Transmitter output buffer
High-speed serial clock used by the serializer
Slow-speed reference clock used by the receiver
Slow-speed clock used by the logic array (divisible by two for
double-width mode)
2–2). Data travels through the Stratix GX transmitter via the
Figure 2–3
is a block diagram of the transmitter
Stratix GX Device Handbook, Volume 1
for more information about the inter-
Stratix GX Transceivers
2–5