EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 194

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration
5–2
Stratix GX Device Handbook, Volume 1
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
A built-in weak pull-up resistor pulls all user I/O pins to V
and during device configuration.
SRAM configuration elements allow Stratix GX devices to be
reconfigured in-circuit by loading new configuration data into the device.
With real-time reconfiguration, the device is forced into command mode
with a device pin. The configuration process loads different configuration
data, reinitializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
Configuration Schemes
You can load the configuration data for a Stratix GX device with one of
five configuration schemes (see
target application. You can use a configuration device, intelligent
controller, or the JTAG port to configure a Stratix GX device. A
configuration device can automatically configure a Stratix GX device at
system power-up.
You can configure multiple Stratix GX devices in any of five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device.
Configuration device
Passive serial (PS)
Passive parallel
asynchronous (PPA)
Fast passive parallel
JTAG
Table 5–1. Data Sources for Configuration
Configuration Scheme
Enhanced or EPC2 configuration device
ByteBlasterMV™ or MasterBlaster™ download
cable or serial data source
Parallel data source
Parallel data source
MasterBlaster or ByteBlasterMV download cable
or a microprocessor with a Jam or JBC file (.jam
or .jbc)
Table
5–1), chosen on the basis of the
Data Source
Altera Corporation
February 2005
CCIO
before