EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 23

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Pre-emphasis percentage is defined as V
differential emphasized voltage (peak-to-peak) and V
steady-state voltage (peak-to-peak).
Programmable Transmitter Termination
The programmable termination can be statically set in the Quartus II
software. The values are 100 Ω , 120 Ω , 150 Ω , and off.
setup for programmable termination.
Figure 2–9. Programmable Transmitter Termination
Receiver Path
This section describes the data path through the Stratix GX receiver (refer
to
via the following modules:
■
■
■
■
■
■
■
Receiver Input Buffer
The Stratix GX receiver input buffer supports the 1.5-V PCML I/O
standard at a rate up to 3.1875 Gbps. Additional I/O standards, LVDS,
3.3-V PCML, and LVPECL can be supported when AC coupled. The
common mode of the input buffer is 1.1 V. The receiver can support
Stratix GX-to-Stratix GX DC coupling.
Figure 2–2 on page
Input buffer
Clock Recovery Unit (CRU)
Deserializer
Pattern detector and word aligner
Rate matcher and channel aligner
8B/10B decoder
Receiver logic array interface
Programmable
Output
Driver
2–4). Data travels through the Stratix GX receiver
V
CM
Stratix GX Device Handbook, Volume 1
PP
/V
S
– 1, where V
Stratix GX Transceivers
50, 60, or 75
Figure 2–9
S
is the differential
PP
is the
shows the
2–13