EP1SGX10DF672C5N Altera, EP1SGX10DF672C5N Datasheet - Page 4

• Manufacturer Part Number: EP1SGX10DF672C5N
• Description: IC STRATIX GX FPGA 10KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX10DF672C5N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 362
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Features
1–2
Stratix GX Device Handbook, Volume 1
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FPGA features are as follows:
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Pattern detector and word aligner supports programmable
patterns
8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-
to 8-bit decoding
Rate matcher compliant with IEEE 802.3-2002 for GigE mode
and with IEEE 802-3ae for XAUI mode
Channel bonding compliant with IEEE 802.3ae (for XAUI mode
only)
Device can bypass some transceiver block features if necessary
10,570 to 41,250 logic elements (LEs); see
Up to 3,423,744 RAM bits (427,968 bytes) available without
reducing logic resources
TriMatrix
implement true dual-port memory and first-in-out (FIFO)
buffers
Up to 16 global clock networks with up to 22 regional clock
networks per device region
High-speed DSP blocks provide dedicated implementation of
multipliers (faster than 300 MHz), multiply-accumulate
functions, and finite impulse response (FIR) filters
Up to eight general usage phase-locked loops (four enhanced
PLLs and four fast PLLs) per device provide spread spectrum,
programmable bandwidth, clock switchover, real-time PLL
reconfiguration, and advanced multiplication and phase
shifting
Support for numerous single-ended and differential I/O
standards
High-speed source-synchronous differential I/O support on up
to 45 channels for 1-Gbps performance
Support for source-synchronous bus standards, including
10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,
Network Packet Streaming Interface (NPSI), HyperTransport
technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)
SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM
(FCRAM), and single data rate (SDR) SDRAM
Support for multiple intellectual property megafunctions from
Altera
Program (AMPP
Support for remote configuration updates
Dynamic phase alignment on LVDS receiver channels
®
MegaCore
™
memory consisting of three RAM block sizes to
SM
®
) megafunctions
functions and Altera Megafunction Partners
Table 1–1
Altera Corporation
February 2005
TM