DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet
DF61654N50FTV
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DF61654N50FTV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8SX/1653 Group 32 Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series H8SX/1653 R5F61653 H8SX/1654 R5F61654 Rev.1.00 2005.09 ...
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Rev.1.00 Sep. 08, 2005 Page ii of xlviii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8SX/1653 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S ...
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H8SX/1653 Group manuals: Document Title H8SX/1653 Group Hardware Manual H8SX Family Software Manual Document No. This manual REJ09B0102 Rev.1.00 Sep. 08, 2005 Page vii of xlviiil ...
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Rev.1.00 Sep. 08, 2005 Page viii of xlviii ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram ....................................................................................................................... 2 1.3 Pin Assignments..................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Configuration in Each Operating Mode.............................................................. 4 1.3.3 Pin Functions ............................................................................................................ 8 Section 2 CPU......................................................................................................17 2.1 Features................................................................................................................................ 17 2.2 ...
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Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) ..................................................................................................... 52 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 52 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ...
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Address Error Source.............................................................................................. 80 4.5.2 Address Error Exception Handling ......................................................................... 81 4.6 Interrupts.............................................................................................................................. 82 4.6.1 Interrupt Sources..................................................................................................... 82 4.6.2 Interrupt Exception Handling ................................................................................. 83 4.7 Instruction Exception Handling ........................................................................................... 83 4.7.1 Trap Instruction....................................................................................................... 83 4.7.2 Exception Handling by Illegal ...
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Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123 5.8.6 Interrupts of Peripheral Modules .......................................................................... 124 Section 6 Bus Controller (BSC) ........................................................................ 125 6.1 Features.............................................................................................................................. 125 6.2 Register Descriptions......................................................................................................... 128 6.2.1 Bus Width Control Register (ABWCR) ............................................................... 129 6.2.2 ...
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Wait Control ......................................................................................................... 189 6.7.6 Read Strobe (RD).................................................................................................. 191 6.7.7 Extension of Chip Select (CS) Assertion Period................................................... 191 DACK Signal Output Timing ............................................................................... 191 6.7.8 6.8 Burst ROM Interface.......................................................................................................... 193 6.8.1 Burst ROM Space Setting..................................................................................... 193 6.8.2 Data Bus................................................................................................................ ...
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Section 7 DMA Controller (DMAC)................................................................. 229 7.1 Features.............................................................................................................................. 229 7.2 Input/Output Pins............................................................................................................... 232 7.3 Register Descriptions......................................................................................................... 233 7.3.1 DMA Source Address Register (DSAR) .............................................................. 234 7.3.2 DMA Destination Address Register (DDAR) ...................................................... 235 7.3.3 DMA Offset Register (DOFR).............................................................................. 236 7.3.4 ...
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DTC Transfer Count Register B (CRB)................................................................ 314 8.2.7 DTC enable registers and H (DTCERA to DTCERE, DTCERG, and DTCERH) ...................................................................................................... 314 8.2.8 DTC Control Register (DTCCR) .......................................................................... 315 8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 317 ...
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Port Register (PORTn and M)........................ 349 9.1.4 Input Buffer Control Register (PnICR and ...
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Timer Status Register (TSR)................................................................................. 429 10.3.6 Timer Counter (TCNT)......................................................................................... 432 10.3.7 Timer General Register (TGR) ............................................................................. 432 10.3.8 Timer Start Register (TSTR) ................................................................................ 433 10.3.9 Timer Synchronous Register (TSYR)................................................................... 434 10.4 Operation ........................................................................................................................... 435 10.4.1 Basic Functions..................................................................................................... 435 10.4.2 ...
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Next Data Registers H, L (NDRH, NDRL) .......................................................... 484 11.3.4 PPG Output Control Register (PCR) .................................................................... 486 11.3.5 PPG Output Mode Register (PMR) ...................................................................... 487 11.4 Operation ........................................................................................................................... 488 11.4.1 Output Timing ...................................................................................................... 489 11.4.2 Sample Setup Procedure for ...
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Interrupt Sources................................................................................................................ 524 12.7.1 Interrupt Sources and DTC Activation ................................................................. 524 12.7.2 A/D Converter Activation..................................................................................... 525 12.8 Usage Notes ....................................................................................................................... 526 12.8.1 Notes on Setting Cycle.......................................................................................... 526 12.8.2 Conflict between TCNT Write and Counter Clear................................................ 526 12.8.3 Conflict between ...
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Transmit Data Register (TDR).............................................................................. 552 14.3.4 Transmit Shift Register (TSR) .............................................................................. 552 14.3.5 Serial Mode Register (SMR) ................................................................................ 552 14.3.6 Serial Control Register (SCR) .............................................................................. 556 14.3.7 Serial Status Register (SSR) ................................................................................. 561 14.3.8 Smart Card Mode Register (SCMR)..................................................................... ...
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Interrupts in Smart Card Interface Mode .............................................................. 625 14.10 Usage Notes ....................................................................................................................... 627 14.10.1 Module Stop Mode Setting ................................................................................... 627 14.10.2 Break Detection and Processing ........................................................................... 627 14.10.3 Mark State and Break Detection ........................................................................... 627 14.10.4 Receive Error Flags ...
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DMA Transfer Setting Register (DMA) ............................................................... 658 15.3.22 Endpoint Stall Register (EPSTL).......................................................................... 661 15.3.23 Configuration Value Register (CVR) ................................................................... 662 15.3.24 Control Register (CTLR) ...................................................................................... 662 15.3.25 Endpoint Information Register (EPIR) ................................................................. 664 15.3.26 Transceiver Test Register 0 (TRNTREG0) ...
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I C Bus Control Register A (ICCRA) ................................................................... 707 2 16.3 Bus Control Register B (ICCRB).................................................................... 708 2 16.3 Bus Mode Register (ICMR)............................................................................ 710 2 16.3 Bus Interrupt Enable Register (ICIER) ........................................................... ...
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Notes on Board Design ......................................................................................... 750 17.7.6 Notes on Noise Countermeasures ......................................................................... 750 17.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 751 Section 18 D/A Converter ................................................................................. 753 18.1 Features.............................................................................................................................. 753 18.2 Input/Output Pins............................................................................................................... 754 18.3 Register ...
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Standard Serial Communication Interface Specifications for Boot Mode ......................... 816 20.12 Usage Notes ....................................................................................................................... 841 Section 21 Clock Pulse Generator .....................................................................843 21.1 Register Description........................................................................................................... 845 21.1.1 System Clock Control Register (SCKCR) ............................................................ 845 21.2 Oscillator............................................................................................................................ 848 21.2.1 Connecting Crystal ...
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Bφ Clock Output Control................................................................................................... 874 22.10 Usage Notes ....................................................................................................................... 875 22.10.1 I/O Port Status....................................................................................................... 875 22.10.2 Current Consumption during Oscillation Settling Standby Period ....................... 875 22.10.3 Module Stop Mode of DMAC or DTC................................................................. 875 22.10.4 On-Chip Peripheral Module Interrupts ...
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Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 2 Figure 1.2 Pin Assignments ............................................................................................................ 3 Section 2 CPU Figure 2.1 CPU Operating Modes ................................................................................................ 19 Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 20 Figure 2.3 Stack Structure (Normal Mode) .................................................................................. ...
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Figure 5.5 Interrupt Exception Handling.................................................................................... 114 Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller ....................................... 117 Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 122 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller.............................................................................. 127 ...
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Figure 6.32 Access Timing of 3 Address Cycles (ADDEX = 1) ................................................ 202 Figure 6.33 Read Strobe Timing................................................................................................. 204 Figure 6.34 Chip Select (CS) Assertion Period Extension Timing in Data Cycle ...................... 205 Figure 6.35 Consecutive Read Accesses to Same ...
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Figure 7.22 Example of Timing for Channel Priority................................................................. 281 Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 282 Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 283 Figure 7.25 Example of Transfer in Normal ...
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Figure 8.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area) .......................................... 329 Figure 8.10 Operation of Chain Transfer.................................................................................... 330 Figure 8.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or ...
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Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 458 Figure 10.29 Phase Counting Mode Application Example......................................................... 460 Figure 10.30 Count Timing in Internal Clock Operation............................................................ 464 Figure 10.31 Count Timing in External Clock Operation .......................................................... 464 Figure 10.32 ...
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Section 12 8-Bit Timers (TMR) Figure 12.1 Block Diagram of 8-Bit Timer Module (Unit 0) ..................................................... 502 Figure 12.2 Block Diagram of 8-Bit Timer Module (Unit 1) ..................................................... 503 Figure 12.3 Block Diagram of 8-Bit Timer Module (Unit 2) ..................................................... ...
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Figure 14.9 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 591 Figure 14.10 Example of Serial Transmission Flowchart........................................................... 592 Figure 14.11 Example of SCI Operation for Reception (Example with 8-Bit Data, ...
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Figure 14.41 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission) (Setting is Prohibited in SCI_5 and SCI_6) ................................... 631 Figure 14.42 Sample Flowchart for Mode Transition during Reception .................................... 631 Figure 14.43 Block Diagram of CRC Operation ...
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Figure 16.5 Master Transmit Mode Operation Timing 1............................................................ 720 Figure 16.6 Master Transmit Mode Operation Timing 2............................................................ 720 Figure 16.7 Master Receive Mode Operation Timing 1 ............................................................. 722 Figure 16.8 Master Receive Mode Operation Timing 2 ............................................................. 723 Figure 16.9 ...
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Figure 20.10 USB Boot Mode State Transition Diagram ........................................................... 795 Figure 20.11 Programming/Erasing Flow................................................................................... 797 Figure 20.12 RAM Map when Programming/Erasing is Executed ............................................ 798 Figure 20.13 Programming Procedure in User Program Mode .................................................. 799 Figure 20.14 Erasing Procedure in ...
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Section 24 Electrical Characteristics Figure 24.1 Output Load Circuit ................................................................................................ 921 Figure 24.2 External Bus Clock Timing..................................................................................... 922 Figure 24.3 Oscillation Settling Timing after Software Standby Mode ..................................... 922 Figure 24.4 Oscillation Settling Timing ..................................................................................... 923 Figure 24.5 External Input ...
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Figure 24.37 Data Signal Timing ............................................................................................... 949 Figure 24.38 Load Condition...................................................................................................... 949 Appendix Figure C.1 Package Dimensions (TFP-120) ............................................................................... 959 Rev.1.00 Sep. 08, 2005 Page xxxix of xlviii ...
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Rev.1.00 Sep. 08, 2005 Page xl of xlviii ...
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Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode.............................................................. 4 Table 1.2 Pin Functions ............................................................................................................ 8 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 34 Table 2.2 Combinations of Instructions and Addressing Modes (1)....................................... 36 Table 2.2 Combinations ...
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Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 89 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 105 Table 5.3 Interrupt Control Modes ....................................................................................... 110 Table 5.4 Interrupt Response Times ..................................................................................... 115 Table 5.5 Number of Execution States ...
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Table 7.3 Settings and Areas of Extended Repeat Area ....................................................... 253 Table 7.4 Transfer Modes ..................................................................................................... 254 Table 7.5 List of On-chip module interrupts to DMAC........................................................ 265 Table 7.6 Priority among DMAC Channels.......................................................................... 280 Table 7.7 Interrupt Sources and Priority............................................................................... ...
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Table 10.16 TIOR_2............................................................................................................. 414 Table 10.17 TIORH_3 .......................................................................................................... 415 Table 10.18 TIORL_3 .......................................................................................................... 416 Table 10.19 TIOR_4............................................................................................................. 417 Table 10.20 TIOR_5............................................................................................................. 418 Table 10.21 TIORH_0 .......................................................................................................... 419 Table 10.22 TIORL_0 .......................................................................................................... 420 Table 10.23 TIOR_1............................................................................................................. 421 Table 10.24 TIOR_2............................................................................................................. 422 ...
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Table 14.3 Relationships between N Setting in BRR and Bit Rate B..................................... 569 Table 14.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 570 Table 14.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) ...
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Section 18 D/A Converter Table 18.1 Pin Configuration.................................................................................................. 754 Table 18.2 Control of D/A Conversion................................................................................... 756 Section 20 Flash Memory (0.18-mm F-ZTAT Version) Table 20.1 Differences between Boot Mode, User Program Mode, and Programmer Mode ......................................................................................... 764 Table 20.2 Pin ...
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Table 24.6 Bus Timing (2)...................................................................................................... 927 Table 24.7 DMAC Timing...................................................................................................... 940 Table 24.8 Timing of On-Chip Peripheral Modules ............................................................... 943 Table 24.9 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD− pin characteristics)........................................................................ 948 Table 24.10 A/D Conversion Characteristics........................................................................ ...
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Rev.1.00 Sep. 08, 2005 Page xlviii of xlviii ...
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Features • 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Object programs for those CPUs are executable Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions DMA controller (DMAC) Data ...
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Section 1 Overview Package TQFP-120 Note: Pb-free version * 1.2 Block Diagram RAM ROM H8SX CPU DTC Clock pulse generator [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller WDT: Watchdog timer TMR: 8-bit ...
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Pin Assignments 1.3.1 Pin Assignments P62/TMO2/SCK4/DACK2/IRQ10-B/TRST 91 PLLVcc 92 P63/TMRI3/DREQ3/IRQ11-B/TMS 93 PLLVss 94 P64/TMCI3/TEND3/TDI 95 P65/TMO3/DACK3/TCK 96 MD0 97 P50/AN0/IRQ0-B 98 P51/AN1/IRQ1-B 99 P52/AN2/IRQ2-B 100 AVcc 101 P53/AN3/IRQ3-B 102 AVss 103 P54/AN4/IRQ4-B 104 Vref 105 P55/AN5/IRQ5-B 106 P56/AN6/DA0/IRQ6-B 107 ...
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Section 1 Overview 1.3.2 Pin Configuration in Each Operating Mode Table 1.1 Pin Configuration in Each Operating Mode Pin No. Modes PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B 2 PB2/CS2-A/CS6-A 3 PB3/CS3/CS7-A 4 MD2 5 PM0/TxD6 6 PM1/RxD6 7 PM2 8 PF4/A20 ...
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Pin No. Modes PD2/A2 31 PD1/A1 32 PD0/A0 33 EMLE 34 PM3 35 PM4 36 DrVCC 37 USD+ 38 USD- 39 DrVSS 40 VBUS 41 MD_CLK P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8 P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A ...
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Section 1 Overview Pin No. Modes PH7/ PI0/D8 64 PI1/D9 65 PI2/D10 66 PI3/D11 PI4/D12 69 PI5/D13 70 PI6/D14 71 PI7/D15 72 P10/TxD2/DREQ0-A/IRQ0-A 73 P11/RxD2/TEND0-A/IRQ1-A 74 P12/SCK2/DACK0-A/IRQ2-A 75 ...
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Pin No. Modes P62/TMO2/SCK4/DACK2/IRQ10-B/TRST 92 PLLV CC 93 P63/TMRI3/DREQ3/IRQ11-B/TMS 94 PLLV SS 95 P64/TMCI3/TEND3/TDI 96 P65/TMO3/DACK3/TCK 97 MD0 98 P50/AN0/IRQ0-B 99 P51/AN1/IRQ1-B 100 P52/AN2/IRQ2-B 101 AV CC 102 P53/AN3/IRQ3-B 103 AV SS 104 P54/AN4/IRQ4-B 105 Vref ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Classification Abbreviation Power supply PLLV CC PLLV SS DrVCC DrVSS Clock XTAL EXTAL Bφ Operating mode MD2 control MD1 MD0 MD_CLK RES System control ...
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Classification Abbreviation On-chip TRST emulator TMS TDI TCK TDO Address bus A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Data bus D15 D14 D13 D12 D11 D10 ...
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Section 1 Overview Classification Abbreviation BREQ Bus control BREQO BACK Bus control BS-A/BS RD/WR-A LHWR LLWR LUB LLB Rev.1.00 Sep. 08, 2005 Page 10 of 966 REJ09B0219-0100 Pin No. (TFP-120) I/O Description 112 Input External bus masters ...
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Classification Abbreviation CS0 Bus control CS1 CS2-A/CS2-B CS3 CS4 CS5-A/CS5-B CS6-A/CS6-B CS7-A/CS7-B WAIT Interrupt NMI IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DREQ0-A DMA controller DREQ1-A (DMAC) DREQ2 DREQ3 DACK0-A DACK1-A DACK2 DACK3 TEND0-A TEND1-A ...
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Section 1 Overview Classification Abbreviation 16-bit timer TCLKA-B pulse unit TCLKB-B (TPU) TCLKC-B TCLKD-B TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Programmable PO7 pulse generator PO6 (PPG) PO5 PO4 PO3 PO2 PO1 PO0 8-bit timer TMO0 (TMR) TMO1 TMO2 ...
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Classification Abbreviation Serial TxD0 communication TxD1 interface (SCI) TxD2 TxD4 TxD5 TxD6 RxD0 RxD1 RxD2 RxD4 RxD5 RxD6 SCK0 SCK1 SCK2 SCK4 SCI with IrDA IrTxD (SCI) IrRxD bus interface SCL0, SCL1 2 (IIC2) SDA0, SDA1 Universal ...
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Section 1 Overview Classification Abbreviation A/D converter AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG0 D/A converter DA1 DA0 A/D converter D/A converter AV SS Vref I/O port P17 P16 P15 P14 P13 P12 P11 P10 P27 ...
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Classification Abbreviation I/O port P57 P56 P55 P54 P53 P52 P51 P50 P65 P64 P63 P62 P61 P60 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Pin No. ...
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Section 1 Overview Classification Abbreviation I/O port PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF4 PF3 PF2 PF1 PF0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PM4 PM3 PM2 PM1 ...
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The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
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Section 2 CPU • Two base registers Vector base register Short address base register • 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes • High-speed operation All frequently-used instructions executed in one or two ...
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CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. CPU operating modes 2.2.1 Normal Mode The exception vector table and stack ...
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Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...
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Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...
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Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
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Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...
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Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
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Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
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Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
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General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. SP (ER7) 2.5.2 Program Counter (PC) ...
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Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can ...
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Section 2 CPU Initial Bit Bit Name Value 2 Z Undefined R Undefined R Undefined R/W 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask ...
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Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for ...
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Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...
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Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...
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Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 5 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword size Notes: 1. ...
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Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L ...
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Classifi- cation Instruction Size Arithmetic MULXS, B/W operations DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B MAC — CLRMAC — LDMAC — STMAC — Logic AND, OR, XOR B operations B B W/L NOT B W/L ...
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Section 2 CPU Classifi- cation Instruction Size Bit BFLD B manipu- BFST B lation 8 Branch BRA/BS, BRA/BC BSR/BS, BSR/BC* B System LDC B/W* control (CCR, EXR) LDC L (VBR, SBR) STC B/W* (CCR, EXR) STC L (VBR, ...
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Table 2.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size — Branch BRA/BS, BRA/BC — BSR/BS, BSR/BC — Bcc — BRA — BRA/S — JMP — BSR — JSR — RTS, RTS/L — System TRAPA control — ...
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Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...
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Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE → (EAs) MOVTPE* B @SP+ → Rn POP W/L ...
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Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...
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Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...
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Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVU W/L Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient bits ÷ 32 bits → 32-bit quotient. ...
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Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) AND B/W/L Performs a logical AND operation on data between immediate data, general registers, and memory. (EAd) ∨ #IMM → (EAd), (EAd) ...
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Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...
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Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR B ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in ...
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Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...
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Table 2.11 System Control Instructions Instruction Size Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. RTE/L — Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP — Causes ...
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Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
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Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...
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Section 2 CPU 2.8.2 Register Indirect—@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In ...
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Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− • Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ...
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Section 2 CPU Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is ...
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Immediate—#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate ...
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Section 2 CPU 2.8.10 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed 8-bit absolute address in ...
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Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of ...
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Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...
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Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...
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Section 2 CPU Rev.1.00 Sep. 08, 2005 Page 60 of 966 REJ09B0219-0100 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has five operating modes (modes and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Table 3.1 lists MCU ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When ...
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Bit Bit Name Initial Value R/W 3 Undefined* 2 Undefined* 1 Undefined* 0 Undefined* Note: Determined by pins MD2 to MD0. * Table 3.2 ...
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Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit 15 14 Bit ...
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Initial Bit Bit Name Value 10 Undefined 9 EXPE Undefined 8 RAME 1 All 0 1 DTCMD 1 Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. 2. ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 2 This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash ...
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Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access ...
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Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.3 lists the pin functions in each operating mode. Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode) Port Port A PA7 PA5 to PA3 PA6, PA2 to PA0 Port ...
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Address Map 3.4.1 Address Map Figures 3.1 and 3.2 show the address map in each operating mode. (Advanced mode) H'000000 On-chip ROM H'060000 External address space/ reserved area* H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area* H'FF0000 ...
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Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FF0000 Access prohibited area H'FF2000 On-chip RAM/ external address 2 space* H'FFC000 External address ...
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Mode 2 Boot mode (Advanced mode) H'000000 On-chip ROM H'080000 External address space/ reserved area* H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area* H'FF0000 Access prohibited area H'FF2000 On-chip RAM* H'FFC000 External address space/ reserved area* H'FFEA00 On-chip ...
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Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FF0000 Access prohibited area H'FF2000 On-chip RAM/ external address 2 space* H'FFC000 External address ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and an illegal instruction (general illegal instruction or slot ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...
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Exception Source Reserved for system use User area (not used) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. ...
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Section 4 Exception Handling Table 4.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + ...
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Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
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Section 4 Exception Handling Bφ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For ...
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Section 4 Exception Handling 4.5 Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Instruction ...
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Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents ...
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Section 4 Exception Handling 4.6 Interrupts 4.6.1 Interrupt Sources Interrupt sources are NMI, sleep interrupt, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source NMI NMI pin (external input) Sleep interrupt ...
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Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI or sleep interrupt to eight priority/mask levels to enable multiple-interrupt control. The source to ...
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Section 4 Exception Handling Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling Interrupt Control Mode 0 2 [Legend] 1: Set Cleared to 0 : Retains the previous value. 4.7.2 Exception Handling by Illegal ...
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Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling Interrupt Control Mode 0 2 [Legend] 1: Set Cleared to 0 : Retains the previous value. 4.8 Stack Status after Exception Handling Figure 4.3 shows ...
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Section 4 Exception Handling 4.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISCR IER Internal interrupt sources Source selector WOVI to RESUME DTCER [Legend] ...
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Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ11 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7 6 Bit Name Initial Value Initial Bit Bit Name Value 7 ...
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CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC and DMAC transfer. The ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits * cannot be modified. ...
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Initial Bit Bit Name Value IPR14 1 13 IPR13 1 12 IPR12 1 IPR10 1 9 IPR9 1 8 IPR8 1 R/W Description R Reserved This is a read-only ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 6 IPR6 1 5 IPR5 1 4 IPR4 1 IPR2 1 1 IPR1 1 0 IPR0 1 Rev.1.00 Sep. 08, 2005 Page 94 of 966 REJ09B0219-0100 R/W ...
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IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ11 to IRQ0. Bit 15 14 Bit Name Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ7E IRQ6E Initial Value 0 0 R/W R/W R/W ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source ...
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ISCRL Bit 15 14 Bit Name IRQ7SR IRQ7SF Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ3SR IRQ3SF Initial Value 0 0 R/W R/W R/W • ISCRH Initial Bit Bit Name Value ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 3 IRQ9SR 0 2 IRQ9SF 0 1 IRQ8SR 0 0 IRQ8SF 0 • ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 ...
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Initial Bit Bit Name Value 11 IRQ5SR 0 10 IRQ5SF 0 9 IRQ4SR 0 8 IRQ4SF 0 7 IRQ3SR 0 6 IRQ3SF 0 5 IRQ2SR 0 4 IRQ2SF 0 R/W Description R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 Rev.1.00 Sep. 08, 2005 Page 100 of 966 REJ09B0219-0100 R/W Description R/W IRQ1 Sense Control Rise IRQ1 Sense Control ...
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IRQ Status Register (ISR) ISR is an IRQ11 to IRQ0 interrupt request register. Bit 15 14 Bit Name Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ7F IRQ6F Initial Value 0 0 R/W R/(W)* R/(W)* ...
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Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ11 to IRQ0. The IRQ interrupt used to leave software standby mode should not be set as ...
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Interrupt Sources 5.4.1 External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always ...
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Section 5 Interrupt Controller A block diagram of interrupts IRQn is shown in figure 5.2. Corresponding bit in ICR Input buffer IRQn input [Legend Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing ...
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Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, ...
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Section 5 Interrupt Controller Classification Interrupt Source Reserved for system use A/D ADI Reserved for system use TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D ...
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Classification Interrupt Source TPU_5 TGI5A TGI5B TCI5V TCI5U Reserved for system use TMR_0 CMI0A CMI0B OV0I TMR_1 CMI1A CMI1B OV1I TMR_2 CMI2A CMI2B OV2I TMR_3 CMI3A CMI3B OV3I DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 Reserved for system use DMAC ...
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Section 5 Interrupt Controller Classification Interrupt Source Reserved for system use SCI_0 ERI0 RXI0 TXI0 TEI0 SCI_1 ERI1 RXI1 TXI1 TEI1 SCI_2 ERI2 RXI2 TXI2 TEI2 Reserved for system use SCI_4 ERI4 RXI4 TXI4 TEI4 Reserved for ...
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Classification Interrupt Source IIC2 IICI0 Reserved for system use IICI1 Reserved for system use SCI_5 RXI5 TXI5 ERI5 TEI5 SCI_6 RXI6 TXI6 ERI6 TEI6 TMR_4 CMIA4 or CMIB4 228 TMR_5 CMIA5 or CMIB5 229 TMR_6 CMIA6 or CMIB6 230 TMR_7 ...
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Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 5.3 Flowchart of Procedure ...
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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI and sleep interrupt are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and ...
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Program execution state Interrupt generated? Yes NMI or sleep interrupt No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask ...
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area ...
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Interrupt Response Times Table 5.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are ...
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Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation [Legend] m: Number of wait cycles in an ...
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Interrupt request On-chip peripheral Interrupt request module clear signal Interrupt request IRQ interrupt Interrupt request clear signal Interrupt controller Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Sources The activation source for each DMAC ...
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Section 5 Interrupt Controller (2) Priority Determination The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt Sources, ...
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CPU Priority Control Function Over DTC and DMAC The interrupt controller has a function to control the priority among the DTC, DMAC, and the CPU by assigning different priority levels to the DTC, DMAC, and CPU. Since the priority ...
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Section 5 Interrupt Controller The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in ...
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Table 5.8 shows a setting example of the priority control function over the DTC and DMAC and the transfer request control state. A priority level can be independently set to each DMAC channel, but the table only shows one channel ...
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Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable ...
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Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the ...
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Section 5 Interrupt Controller 5.8.6 Interrupts of Peripheral Modules To clear an interrupt request flag by the CPU, the flag should be read from after clearing if the peripheral module clock is generated by dividing the system clock. This makes ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus ...
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Section 6 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be ...
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A block diagram of the bus controller is shown in figure 6.1. CPU address bus DMAC address bus DTC address bus Internal bus control signals CPU bus mastership acknowledge signal DTC bus mastership acknowledge signal DMAC bus mastership acknowledge signal ...
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Section 6 Bus Controller (BSC) 6.2 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • ...
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Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit 15 14 Bit Name ABWH7 ABWH6 Initial Value 1 1 R/W R/W R/W Bit 7 6 Bit Name ABWL7 ...
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Section 6 Bus Controller (BSC) 6.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit 15 14 Bit Name AST7 ...
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Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA Bit 15 14 Bit Name W72 Initial Value 0 1 R/W ...
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Section 6 Bus Controller (BSC) • WTCRA Initial Bit Bit Name Value W72 1 13 W71 1 12 W70 1 W62 1 9 W61 1 8 W60 1 Rev.1.00 ...
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Initial Bit Bit Name Value 6 W52 1 5 W51 1 4 W50 1 W42 1 1 W41 1 0 W40 1 R/W Description R/W Area 5 Wait Control R/W These bits select ...
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Section 6 Bus Controller (BSC) • WTCRB Initial Bit Bit Name Value W32 1 13 W31 1 12 W30 1 W22 1 9 W21 1 8 W20 1 Rev.1.00 ...
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Initial Bit Bit Name Value 6 W12 1 5 W11 1 4 W10 1 W02 1 1 W01 1 0 W00 1 R/W Description R/W Area 1 Wait Control R/W These bits select ...
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Section 6 Bus Controller (BSC) 6.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O ...
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B RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) CS Assertion Period Control Registers (CSACR) 6.2.5 CSACR selects whether or not the assertion periods of the chip ...
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Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 15 CSXH7 0 14 CSXH6 0 13 CSXH5 0 12 CSXH4 0 11 CSXH3 0 10 CSXH2 0 9 CSXH1 0 8 CSXH0 0 7 CSXT7 0 6 CSXT6 0 ...
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T B Address CSn AS BS RD/WR RD Read Data bus LHWR, LLWR Write Data bus Figure 6.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0) Bus cycle T T ...
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Section 6 Bus Controller (BSC) 6.2.6 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and the number of idle cycles. Bit 15 14 Bit Name IDLS3 IDLS2 Initial Value 1 1 R/W R/W R/W Bit 7 6 ...
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Initial Bit Bit Name Value 12 IDLS0 1 11 IDLCB1 1 10 IDLCB0 1 9 IDLCA1 1 8 IDLCA0 1 7 IDLSEL7 0 6 IDLSEL6 0 5 IDLSEL5 0 4 IDLSEL4 0 3 IDLSEL3 0 2 IDLSEL2 0 1 IDLSEL1 ...
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Section 6 Bus Controller (BSC) 6.2.7 Bus Control Register 1 (BCR1) BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the write data buffer function, and enabling/disabling of the WAIT pin input. Bit 15 14 ...
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Initial Bit Bit Name Value 13, 12 All 0 11, 10 All 0 9 WDBE 0 8 WAITE 0 7 DKC 0 All 0 Note: When external bus release is enabled ...
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Section 6 Bus Controller (BSC) 6.2.8 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU, DMAC, and DTC, and enabling/disabling of the write data buffer function to the peripheral modules. Bit 7 6 Bit ...
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Endian Control Register (ENDIANCR) ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address ...
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Section 6 Bus Controller (BSC) 6.2.10 SRAM Mode Control Register (SRAMCR) SRAMCR specifies the bus interface of each area in the external address space as a basic bus interface or a byte control SRAM interface. In areas specified as 8-bit ...
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Burst ROM Interface Control Register (BROMCR) BROMCR specifies the burst ROM interface. Bit 15 14 Bit Name BSRM0 BSTS02 Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name BSRM1 BSTS12 Initial Value 0 0 R/W R/W ...
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Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 9 BSWD01 0 8 BSWD00 0 7 BSRM1 0 6 BSTS12 0 5 BSTS11 0 4 BSTS10 0 All 0 1 BSWD11 0 0 BSWD10 0 Rev.1.00 ...
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Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR specifies the address/data multiplexed I/O interface. Bit 15 14 Bit Name MPXE7 MPXE6 Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name Initial Value ...
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Section 6 Bus Controller (BSC) 6.3 Bus Configuration Figure 6.4 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. • Internal system bus A bus that connects the CPU, ...