DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 186

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.2.4
RDNCR selects the negation timing of the read strobe signal (RD) when reading the external
address spaces specified as a basic bus interface or the address/data multiplexed I/O interface.
Notes: 1. In an external address space which is specified as byte control SRAM interface, the
Rev.1.00 Sep. 08, 2005 Page 136 of 966
REJ09B0219-0100
Bit
15
14
13
12
11
10
9
8
7 to 0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
2. In an external address space which is specified as burst ROM interface, the RDNCR
Bit Name
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0

Read Strobe Timing Control Register (RDNCR)
RDNCR setting is ignored and the same operation when RDNn = 1 is performed.
setting is ignored during CPU read accesses and the same operation when RDNn = 0 is
performed.
RDN7
R/W
15
R
0
7
0
Initial
Value
0
0
0
0
0
0
0
0
All 0
RDN6
R/W
14
R
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
RDN5
R/W
13
R
0
5
0
Description
Read Strobe Timing Control
RDN7 to RDN0 set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an area for
which the RDNn bit is set to 1 is negated one half-
cycle earlier than that for an area for which the RDNn
bit is cleared to 0. The read data setup and hold time
are also given one half-cycle earlier.
0: In an area n read access, the RD signal is negated
1: In an area n read access, the RD signal is negated
(n = 7 to 0)
Reserved
These are read-only bits and cannot be modified.
RDN4
at the end of the read cycle
one half-cycle before the end of the read cycle
R/W
12
R
0
4
0
RDN3
R/W
11
R
3
0
0
RDN2
R/W
10
R
0
2
0
RDN1
R/W
R
9
0
1
0
RDN0
R/W
R
8
0
0
0