DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 498

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
(2)
Figure 10.18 illustrates the operation when counting upon TCNT_5 overflow/underflow has been
set for TCNT_4, TGRA_4 and TGRA_5 have been designated as input capture registers, and the
TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA4 and TIOCA5 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_4, and the lower 16 bits to TGRA_5.
Figure 10.19 illustrates the operation when counting upon TCNT_5 overflow/underflow has been
set for TCNT_4, and phase counting mode has been designated for channel 5.
TCNT_4 is incremented by TCNT_5 overflow and decremented by TCNT_5 underflow.
Rev.1.00 Sep. 08, 2005 Page 448 of 966
REJ09B0219-0100
TCNT_4 clock
TCNT_4
TCNT_5 clock
TCNT_5
TIOCA4, TIOCA5
TGRA_4
TGRA_5
Examples of Cascaded Operation
TCLKC
TCLKD
TCNT_5
TCNT_4
H'FFFF
H'03A1
Figure 10.18 Example of Cascaded Operation (1)
Figure 10.19 Example of Cascaded Operation (2)
FFFD
0000
FFFE
FFFF
0000
H'0000
0001
0001
0002
H'03A2
H'03A2
H'0000
0001
0000
FFFF
H'0001
0000