DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 606

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
14.3.6
SCR is a register that enables/disables the following SCI transfer operations and interrupt requests,
and selects the transfer clock source. For details on interrupt requests, see section 14.9, Interrupt
Sources. Some bits in SCR have different functions in normal mode and smart card interface
mode.
• When SMIF in SCMR = 0
• When SMIF in SCMR = 1
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Rev.1.00 Sep. 08, 2005 Page 556 of 966
REJ09B0219-0100
Bit
7
6
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
TIE
RIE
Serial Control Register (SCR)
R/W
R/W
TIE
TIE
7
0
7
0
Initial
Value
0
0
R/W
R/W
RIE
RIE
6
0
6
0
R/W
R/W
R/W
R/W
R/W
TE
TE
5
0
5
0
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
A TXI interrupt request can be cancelled by reading 1
from the TDRE flag and then clearing the flag to 0, or by
clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI and ERI interrupt requests can be cancelled by
reading 1 from the RDRF, FER, PER, or ORER flag and
then clearing the flag to 0, or by clearing the RIE bit to 0.
R/W
R/W
RE
RE
4
0
4
0
MPIE
MPIE
R/W
R/W
3
0
3
0
TEIE
TEIE
R/W
R/W
2
0
2
0
CKE1
CKE1
R/W
R/W
1
0
1
0
CKE0
CKE0
R/W
R/W
0
0
0
0