DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 194

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.2.8
BCR2 is used for bus arbitration control of the CPU, DMAC, and DTC, and enabling/disabling of
the write data buffer function to the peripheral modules.
Rev.1.00 Sep. 08, 2005 Page 144 of 966
REJ09B0219-0100
Bit
7, 6
5
4
3, 2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
IBCCS
PWDBE
Bus Control Register 2 (BCR2)
R
7
0
Initial
Value
All 0
0
0
All 0
1
0
R
6
0
R/W
R
R/W
R/W
R
R/W
R/W
R/W
5
0
Description
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 0. The write value should
always be 0.
Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 1. The write value should
always be 1.
Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
bus mastership request conflicts with a DMAC or
DTC bus mastership request
IBCCS
R/W
4
0
R
3
0
R
2
0
R/W
1
1
PWDBE
R/W
0
0

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