DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 656

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
Rev.1.00 Sep. 08, 2005 Page 606 of 966
REJ09B0219-0100
Figure 14.19 Example of Operation for Transmission in Clocked Synchronous Mode
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted
Start transmission
Figure 14.20 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
Bit 0
Transfer direction
Bit 1
1 frame
No
No
No
[3]
[2]
[1]
Bit 7
TXI interrupt
request generated
[1] SCI initialization:
[2] SCI state check and transmit data
[3] Serial transmission continuation
Bit 0
The TxD pin is automatically
designated as the transmit data output
pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0. However, the TDRE
flag is checked and cleared
automatically when the DMAC or
DTC is initiated by a transmit data
empty interrupt (TXI) request and
writes data to TDR.
Bit 1
TEI interrupt request
generated
Bit 6
Bit 7