DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 98

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
Table 2.10 Branch Instructions
Rev.1.00 Sep. 08, 2005 Page 48 of 966
REJ09B0219-0100
Instruction
BISTZ
BFLD
BFST
Instruction
BRA/BS
BRA/BC
BSR/BS
BSR/BC
Bcc
BRA/S
JMP
BSR
JSR
RTS
RTS/L
Size
B
B
B
Size
B
B
∼ Z → (<bit-No.> of <EAd>)
Transfers the inverse of the zero flag value to a specified bit in the
contents of a memory location. The bit number is specified by 3-bit
immediate data.
(EAs) (bit field) → Rd
Transfers a specified bit field in memory location contents to the lower bits
of a specified general register.
Rs → (EAd) (bit field)
Transfers the lower bits of a specified general register to a specified bit
field in memory location contents.
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a specified address.
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a subroutine at a specified
address.
Branches to a specified address if the specified condition is satisfied.
Branches unconditionally to a specified address after executing the next
instruction. The next instruction should be a 1-word instruction except for
the block transfer and branch instructions.
Branches unconditionally to a specified address.
Branches to a subroutine at a specified address.
Branches to a subroutine at a specified address.
Returns from a subroutine.
Returns from a subroutine, restoring data from the stack to multiple
general registers.
Function
Function

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