DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 399

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.1.2
DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the
general output port.
The initial value of DR is H'00.
9.1.3
PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid.
When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and
the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the
ICR value.
The initial value of PORT is undefined and is determined based on the port pin state.
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower four bits are valid and the upper four bits are reserved for port B registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
The lower five bits are valid and the upper three bits are reserved for port M registers.
The lower four bits are valid and the upper four bits are reserved for port B registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
The lower five bits are valid and the upper three bits are reserved for port M registers.
Data Register (PnDR) (n = 1, 2, 6, A, B, D to F, H, I, and M)
Port Register (PORTn) (n = 1, 2, 5, 6, A, B, D to F, H, I, and M)
Undefined
Pn7DR
R/W
Pn7
R
7
0
7
Undefined
Pn6DR
R/W
Pn6
R
6
0
6
Undefined
Pn5DR
R/W
Pn5
R
5
0
5
Undefined
Pn4DR
R/W
Pn4
R
4
0
4
Undefined
Pn3DR
R/W
Pn3
R
3
0
3
Rev.1.00 Sep. 08, 2005 Page 349 of 966
Undefined
Pn2DR
R/W
Pn2
R
2
0
2
Undefined
Pn1DR
R/W
Pn1
R
1
0
1
Section 9 I/O Ports
REJ09B0219-0100
Undefined
Pn0DR
R/W
Pn0
R
0
0
0