DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 541

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4.3
Figure 11.5 shows an example in which pulse output is used for cyclic 5-phase pulse output.
1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
2. Write H'F8 to NDERH, and set bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 in PCR to
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRL
TGRA
H'0000
NDRL
PODRL
PO7
PO6
PO5
PO3
TCNT value
PO4
a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
select compare match in the TPU channel set up in the previous step to be the output trigger.
Write output data H'80 in NDRL.
contents are transferred to PODRL and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRL.
Example of Normal Pulse Output (Example of 5-Phase Pulse Output)
00
Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output)
80
TCNT
80
C0
C0
40
40
60
Compare match
60
20
20
30
30
10
Section 11 Programmable Pulse Generator (PPG)
10
18
18
Rev.1.00 Sep. 08, 2005 Page 491 of 966
08
08
88
88
80
80
C0
REJ09B0219-0100
C0
40
Time