DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 934

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 23 List of Registers
Rev.1.00 Sep. 08, 2005 Page 884 of 966
REJ09B0219-0100
Register Name
I
I
I
I
Slave address register_1
I
I
Timer control register_2
Timer control register_3
Timer control/status register_2
Timer control/status register_3
Time constant register A_2
Time constant register A_3
Time constant register B_2
Time constant register B_3
Timer counter_2
Timer counter_3
Timer counter control register_2
Timer counter control register_3
Timer control register_4
Timer mode register_4
Timer I/O control register_4
Timer interrupt enable register_4
Timer status register_4
Timer counter_4
Timer general register A_4
Timer general register B_4
Timer control register_5
Timer mode register_5
Timer I/O control register_5
Timer interrupt enable register_5
Timer status register_5
Timer counter_5
Timer general register A_5
Timer general register B_5
2
2
2
2
2
2
C bus control register B_1
C bus mode register_1
C bus interrupt enable register_1
C bus status register_1
C bus transmit data register_1
C bus receive data register_1
Abbreviation
ICCRB_1
ICIER_1
SAR_1
ICDRT_1
ICDRR_1
TCR_2
TCR_3
TCSR_2
TCSR_3
TCORA_2
TCORA_3
TCORB_2
TCORB_3
TCNT_2
TCNT_3
TCCR_2
TCCR_3
TCR_4
TMDR_4
TIOR_4
TIER_4
TSR_4
TCNT_4
TGRA_4
TGRB_4
TCR_5
TMDR_5
TIOR_5
TIER_5
TSR_5
TCNT_5
TGRA_5
TGRB_5
ICMR_1
ICSR_1
8
8
8
8
16
16
8
8
16
16
Number
of Bits
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
8
8
8
16
Address
H'FFEB9
H'FFEBB
H'FFEBC
H'FFEBD
H'FFEC0
H'FFEC1
H'FFEC2
H'FFEC3
H'FFEC4
H'FFEC5
H'FFEC6
H'FFEC7
H'FFEC8
H'FFEC9
H'FFECA
H'FFECB
H'FFEE0
H'FFEE2
H'FFEE4
H'FFEE8
H'FFEEA
H'FFEF0
H'FFEF1
H'FFEF2
H'FFEF4
H'FFEF5
H'FFEF6
H'FFEF8
H'FFEFA
H'FFEBA
H'FFEBE
H'FFEBF
H'FFEE1
H'FFEE5
H'FFEE6
Module
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
IIC2_1
TMR_2
TMR_3
TMR_2
TMR_3
TMR_2
TMR_3
TMR_2
TMR_3
TMR_2
TMR_3
TMR_2
TMR_3
TPU_4
TPU_4
TPU_4
TPU_4
TPU_4
TPU_4
TPU_4
TPU_4
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
Data
Width
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Access
Cycles
(Read/Write)
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ