DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 707

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.20 FIFO Clear Register (FCLR)
FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
EP3 CLR
EP1 CLR
EP2 CLR
EP0o CLR
EP0i CLR
Undefined
7
Undefined
EP3 CLR
Initial
Value
Undefined 
Undefined W
Undefined W
Undefined W
Undefined 
Undefined W
Undefined W
W
6
Undefined
EP1 CLR
R/W
W
5
Description
Reserved
The write value should always be 0.
EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
Reserved
The write value should always be 0.
EP0o Clear
Writing 1 to this bit initializes the endpoint 0 receive
FIFO buffer.
EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.
Undefined
EP2 CLR
W
4
Undefined
3
Rev.1.00 Sep. 08, 2005 Page 657 of 966
Section 15 USB Function Module (USB)
Undefined
2
EP0o CLR
Undefined
W
1
REJ09B0219-0100
Undefined
EP0i CLR
W
0

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