DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 23

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.10 Usage Notes ....................................................................................................................... 627
14.11 CRC Operation Circuit ...................................................................................................... 632
Section 15 USB Function Module (USB)..........................................................639
15.1 Features.............................................................................................................................. 639
15.2 Input/Output Pins ............................................................................................................... 640
15.3 Register Descriptions ......................................................................................................... 641
14.9.2 Interrupts in Smart Card Interface Mode .............................................................. 625
14.10.1 Module Stop Mode Setting ................................................................................... 627
14.10.2 Break Detection and Processing ........................................................................... 627
14.10.3 Mark State and Break Detection ........................................................................... 627
14.10.4 Receive Error Flags and Transmit Operations
14.10.5 Relation between Writing to TDR and TDRE Flag .............................................. 628
14.10.6 Restrictions on Using DTC or DMAC.................................................................. 628
14.10.7 SCI Operations during Mode Transitions ............................................................. 629
14.11.1 Features................................................................................................................. 632
14.11.2 Register Descriptions............................................................................................ 633
14.11.3 CRC Operation Circuit Operation......................................................................... 635
14.11.4 Note on CRC Operation Circuit............................................................................ 638
15.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 642
15.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 643
15.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 644
15.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 645
15.3.5 Interrupt Select Register 1 (ISR1)......................................................................... 646
15.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 647
15.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 648
15.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 649
15.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 649
15.3.10 EP0i Data Register (EPDR0i)............................................................................... 650
15.3.11 EP0o Data Register (EPDR0o) ............................................................................. 651
15.3.12 EP0s Data Register (EPDR0s) .............................................................................. 651
15.3.13 EP1 Data Register (EPDR1) ................................................................................. 652
15.3.14 EP2 Data Register (EPDR2) ................................................................................. 652
15.3.15 EP3 Data Register (EPDR3) ................................................................................. 653
15.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 653
15.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 654
15.3.18 Trigger Register (TRG)......................................................................................... 654
15.3.19 Data Status Register (DASTS).............................................................................. 656
15.3.20 FIFO Clear Register (FCLR) ................................................................................ 657
(Clocked Synchronous Mode Only) ..................................................................... 627
Rev.1.00 Sep. 08, 2005 Page xxi of xlviiil