DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 480

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.1.00 Sep. 08, 2005 Page 430 of 966
REJ09B0219-0100
Bit
3
2
Bit Name
TGFD
TGFC
Initial
Value
0
0
R/W
R/(W)* Input Capture/Output Compare Flag D
R/(W)* Input Capture/Output Compare Flag C
Description
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When TCNT = TGRD while TGRD is functioning as
output compare register
When TCNT value is transferred to TGRD by input
capture signal while TGRD is functioning as input
capture register
When DTC is activated by a TGID interrupt while
the DISEL bit in MRB of DTC is 0
When 0 is written to TGFD after reading TGFD = 1
When TCNT = TGRC while TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
When DTC is activated by a TGIC interrupt while
the DISEL bit in MRB of DTC is 0
When 0 is written to TGFC after reading TGFC = 1