DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 293

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
19
18
17
Bit Name
ERRF

ESIF
Initial
Value
0
0
0
R/W
R/(W)* System Error Flag
R
R/(W)* Transfer Escape Interrupt Flag
Description
Indicates that an address error or an NMI interrupt has
been generated. This bit is available only in DMDR_0.
Setting this bit to 1 prohibits writing to the DTE bit for all
the channels. This bit is reserved in DMDR_1 to
DMDR_3. It is always read as 0 and cannot be modified.
0: An address error or an NMI interrupt has not been
1: An address error or an NMI interrupt has been
[Clearing condition]
•
[Setting condition]
•
However, when an address error or an NMI interrupt has
been generated in DMAC module stop mode, this bit is
not set to 1.
Reserved
This bit is always read as 0 and cannot be modified.
Indicates that a transfer escape end interrupt has been
requested. A transfer escape end means that a transfer
is terminated before the transfer counter reaches 0.
0: A transfer escape end interrupt has not been
1: A transfer escape end interrupt has been requested
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
generated
generated
requested
When clearing to 0 after reading ERRF = 1
When an address error or an NMI interrupt has been
generated
When setting the DTE bit to 1
When clearing to 0 before reading ESIF = 1
When a transfer size error interrupt is requested
When a repeat size end interrupt is requested
When a transfer end interrupt by an extended repeat
area overflow is requested
Rev.1.00 Sep. 08, 2005 Page 243 of 966
Section 7 DMA Controller (DMAC)
REJ09B0219-0100