DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 210

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.5.4
The type of the external bus interfaces, bus width, endian format, number of access cycles, and
strobe assert/negate timings can be set for each area in the external address space. The bus width
and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and
are not affected by the external bus settings.
(1)
Four types of external bus interfaces are provided and can be selected in area units. Table 6.4
shows each interface name, description, area name to be set for each interface. Table 6.5 shows the
areas that can be specified for each interface. The initial state of each area is a basic bus interface.
Table 6.4
Rev.1.00 Sep. 08, 2005 Page 160 of 966
REJ09B0219-0100
Interface
Basic interface
Byte control SRAM interface
Burst ROM interface
Address/data multiplexed I/O
interface
Type of External Bus Interface
External Bus Interface
B
CS5
CS6
Output waveform
Address bus
Interface Names and Area Names
Figure 6.9 Timing When CS Signal is Output to the Same Pin
Description
Directly connected to ROM and
RAM
Directly connected to byte
SRAM with byte control pin
Directly connected to the ROM
that allows page access
Directly connected to the
peripheral LSI that requires
address and data multiplexing
Area 5 access
Area 5 access
Area 6 access
Area 6 access
Area Name
Basic bus space
Byte control SRAM space
Burst ROM space
Address/data multiplexed I/O
space