DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 271

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.12
6.12.1
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 6.25 shows the number of access cycles for each on-chip memory space.
Table 6.25 Number of Access Cycles for On-Chip Memory Spaces
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
Table 6.26 lists the number of access cycles for registers of on-chip peripheral modules.
Table 6.26 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Access Space
On-chip ROM space
On-chip RAM space
Module to be Accessed
DMAC registers
MCU operating mode, clock pulse generator,
power-down control registers, interrupt controller,
bus controller, and DTC registers
I/O port registers of PFCR and WDT
I/O port registers other than PFCR and PORTM,
TPU, PPG, TMR, SCI, SCI0 to SCI2, SCI4, A/D,
and D/A registers
I/O port registers of PORTM,
USB, SCI5, and SCI6
Internal Bus
Access to Internal Address Space
Access
Read
Write
Read
Write
Number of Cycles
Read
Two Iφ
Two Iφ
Two Pφ
Two Pφ
Three Pφ
Write
Three Iφ Disabled
Three Pφ Disabled
Rev.1.00 Sep. 08, 2005 Page 221 of 966
Three Iφ cycles
One Iφ cycle
Number of Access Cycles
One Iφ cycle
One Iφ cycle
Write Data Buffer Function
Disabled
Enabled
Enabled
Section 6 Bus Controller (BSC)
REJ09B0219-0100