DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 32

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 7.22 Example of Timing for Channel Priority................................................................. 281
Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 282
Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 283
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer
Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 285
Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 286
Figure 7.29 Example of Transfer in Normal Transfer Mode Activated
Figure 7.30 Example of Transfer in Block Transfer Mode Activated
Figure 7.31 Example of Transfer in Normal Transfer Mode Activated
Figure 7.32 Example of Transfer in Block Transfer Mode Activated
Figure 7.33 Example of Transfer in Normal Transfer Mode Activated
Figure 7.34 Example of Transfer in Single Address Mode (Byte Read) .................................... 292
Figure 7.35 Example of Transfer in Single Address Mode (Byte Write) ................................... 293
Figure 7.36 Example of Transfer in Single Address Mode Activated
Figure 7.37 Example of Transfer in Single Address Mode Activated
Figure 7.38 Example of Transfer in Single Address Mode Activated
Figure 7.39 Interrupt and Interrupt Sources................................................................................ 304
Figure 7.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 304
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................. 308
Figure 8.2 Transfer Information on Data Area ........................................................................... 318
Figure 8.3 Correspondence between DTC Vector Address and Transfer Information............... 318
Figure 8.4 Flowchart of DTC Operation .................................................................................... 322
Figure 8.5 Bus Cycle Division Example .................................................................................... 324
Figure 8.6 Transfer Information Read Skip Timing ................................................................... 325
Figure 8.7 Memory Map in Normal Transfer Mode................................................................... 327
Figure 8.8 Memory Map in Repeat Transfer Mode
Rev.1.00 Sep. 08, 2005 Page xxx of xlviii
(When Transfer Source is Specified as Repeat Area)............................................... 328
(Transfer Source DSAR = Odd Address and Source Address Increment).............. 284
Destination DDAR = Odd Address and Destination Address Decrement)............. 284
by DREQ Falling Edge ........................................................................................... 287
by DREQ Falling Edge ........................................................................................... 288
by DREQ Low Level .............................................................................................. 289
by DREQ Low Level .............................................................................................. 290
by DREQ Low Level with NRD = 1 ...................................................................... 291
by DREQ Falling Edge ........................................................................................... 294
by DREQ Low Level .............................................................................................. 295
by DREQ Low Level with NRD = 1 ...................................................................... 296