DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 766

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
16.3.6
SAR is sets the slave address. In slave mode, if the upper 7 bits of SAR match the upper 7 bits of
the first frame received after a start condition, the LSI operates as the slave device.
16.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a
space in the I
to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting
data to ICDRS, continuous transmission is possible.
Rev.1.00 Sep. 08, 2005 Page 716 of 966
REJ09B0219-0100
Bit
7 to 1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Slave Address Register (SAR)
I
2
Bit Name
SVA6 to
SVA0

2
C Bus Transmit Data Register (ICDRT)
C Bus Interface2 (IIC2)
2
C bus shift register, it transfers the transmit data which has been written to ICDRT
SVA6
R/W
R/W
7
0
7
0
Initial
Value
0
0
SVA5
R/W
R/W
6
0
6
0
R/W
R/W
R/W
SVA4
R/W
R/W
5
0
5
0
Description
Slave Address 6 to 0
These bits set a unique address differing from the
addresses of other slave devices connected to the I
bus.
Reserved
Although this bit is readable/writable, only 0 should be
written to.
SVA3
R/W
R/W
4
0
4
0
SVA2
R/W
R/W
3
0
3
0
SVA1
R/W
R/W
2
0
2
0
SVA0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
2
C