DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 619

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.
Table 14.3 Relationships between N Setting in BRR and Bit Rate B
[Legend]
B:
N:
Pφ:
n and S: Determined by the SMR settings shown in the following table.
Table 14.4 shows sample N settings in BRR in normal asynchronous mode. Table 14.5 shows the
maximum bit rate settable for each operating frequency. Tables 14.7 and 14.9 show sample N
settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In
smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be
selected. For details, see section 14.7.4, Receive Data Sampling Timing and Reception Margin.
Tables 14.6 and 14.8 show the maximum bit rates with external clock input.
Mode
Asynchronous
mode
Clocked synchronous mode
Smart card interface mode
CKS1
0
0
1
1
Bit Rate Register (BRR)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
SMR Setting
CKS0
0
1
0
1
ABCS Bit Bit Rate
0
1
B =
B =
N =
N =
n
0
1
2
3
64 × 2
32 × 2
8 × 2
S × 2
P × 10
P × 10
P × 10
P × 10
2n – 1
2n + 1
2n – 1
2n – 1
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
× B
6
6
6
6
× B
× B
× B
BCP1
0
0
1
1
1
1
1
1
Error
Error (%) = {
Error (%) = {
Error (%) =
SMR Setting
Rev.1.00 Sep. 08, 2005 Page 569 of 966
{
B × 64 × 2
B × 32 × 2
BCP0
0
1
0
1
B × S × 2
P × 10
P × 10
2n – 1
2n – 1
2n + 1
P × 10
6
6
× (N + 1)
× (N + 1)
× (N + 1)
REJ09B0219-0100
6
S
32
64
372
256
– 1 } × 100
– 1 } × 100
– 1 × 100
}