DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 861
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.8.2
The software protection protects the flash memory against programming/erasing by disabling
download of the programming/erasing program, using the key code, and by the RAMER setting.
Table 20.12 Software Protection
20.8.3
Error protection is a mechanism for aborting programming or erasure when a CPU runaway
occurs or operations not according to the programming/erasing procedures are detected during
programming/erasing of the flash memory. Aborting programming or erasure in such cases
prevents damage to the flash memory due to excessive programming or erasing.
If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set
to 1 and the error protection state is entered.
• When an interrupt request, such as NMI, occurs during programming/erasing.
• When the flash memory is read from during programming/erasing (including a vector read or
• When a SLEEP instruction is executed (including software-standby mode) during
• When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership
Item
Protection
by SCO bit
Protection
by FKEY
Emulation
protection
an instruction fetch).
programming/erasing.
during programming/erasing.
Software Protection
Error Protection
Description
The programming/erasing protection state is
entered when the SCO bit in FCCS is cleared to 0
to disable download of the programming/erasing
programs.
The programming/erasing protection state is
entered because download and
programming/erasing are disabled unless the
required key code is written in FKEY.
The programming/erasing protection state is
entered when the RAMS bit in the RAM emulation
register (RAMER) is set to 1.
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Rev.1.00 Sep. 08, 2005 Page 811 of 966
Download
O
O
O
Function to be Protected
Programming/
Erasing
O
O
O
REJ09B0219-0100
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