DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 571

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.2
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT
values match, the compare match signal is not generated until the next TCNT clock input. Figure
12.9 shows this timing.
12.5.3
When a compare match signal is generated, the timer output changes as specified by the bits OS3
to OS0 in TCSR. Figure 12.10 shows the timing when the timer output is toggled by the compare
match A signal.
P
Compare match A
signal
Timer output pin
Timing of CMFA and CMFB Setting at Compare Match
Timing of Timer Output at Compare Match
P
TCNT
TCOR
Compare match
signal
CMF
Figure 12.10 Timing of Toggled Timer Output at Compare Match A
Figure 12.9 Timing of CMF Setting at Compare Match
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Rev.1.00 Sep. 08, 2005 Page 521 of 966
Section 12 8-Bit Timers (TMR)
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REJ09B0219-0100