DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 783
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 16.4 Time for Monitoring SCL
16.7
1. Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition.
2. The WAIT bit in the I
CKS3
0
1
The ninth falling edge can be confirmed by monitoring the SCLO bit in the I
register B (ICCRB).
If a stop or a repeated start condition is issued at certain timing in either of the following cases,
the stop or repeated start condition may be issued incorrectly.
The rising time of the SCL signal exceeds the time given in section 16.6, Bit Synchronous
The bit synchronous circuit is activated because a slave device holds the SCL bus low
If the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one
transfer clock cycle during the eighth clock, the high level period of the ninth clock may be
shorter than a given period.
Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance).
during the eighth clock.
Usage Notes
SCL monitor timing
reference clock
SCL
Internal SCL
Figure 16.18 Timing of the Bit Synchronous Circuit
CKS2
0
1
0
1
2
C bus mode register (ICMR) must be held 0.
Time for Monitoring SCL
7.5 tcyc
19.5 tcyc
17.5 tcyc
41.5 tcyc
V
IH
Rev.1.00 Sep. 08, 2005 Page 733 of 966
Section 16 I
2
C Bus Interface2 (IIC2)
2
C bus control
REJ09B0219-0100
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