DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 296

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 DMA Controller (DMAC)
Rev.1.00 Sep. 08, 2005 Page 246 of 966
REJ09B0219-0100
Bit
7
6
5
4, 3
Bit Name
DTF1
DTF0
DTA
Initial
Value
0
0
0
All 0
R/W
R/W
R/W
R/W
R
Description
Data Transfer Factor 1 and 0
Select a DMAC activation source. When the on-chip
peripheral module setting is selected, the interrupt
source should be selected by DMRSR. When the
external request setting is selected, the sampling
method should be selected by the DREQS bit.
00: Auto request (cycle stealing)
01: Auto request (burst access)
10: On-chip module interrupt
11: External request
Data Transfer Acknowledge
This bit is valid in DMA transfer by the on-chip module
interrupt source. This bit enables or disables to clear the
source flag selected by DMRSR.
0: To clear the source in DMA transfer is disabled.
1: To clear the source in DMA transfer is enabled.
Reserved
These bits are always read as 0 and cannot be
modified.
Since the on-chip module interrupt source is not
cleared in DMA transfer, it should be cleared by the
CPU or DTC transfer.
Since the on-chip module interrupt source is cleared
in DMA transfer, it does not require an interrupt by
the CPU or DTC transfer.

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