DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 573

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.6
The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure
12.14 shows the timing of this operation.
12.6
If the bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode).
12.6.1
When the bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
(1)
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
(2)
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by
the TMRI0 pin has been set.
cleared independently.
Setting of Compare Match Flags
Counter Clear Specification
Timing of Overflow Flag (OVF) Setting
Operation with Cascaded Connection
16-Bit Counter Mode
P
TCNT
Overflow signal
OVF
Figure 12.14 Timing of OVF Setting
H'FF
Rev.1.00 Sep. 08, 2005 Page 523 of 966
H'00
Section 12 8-Bit Timers (TMR)
REJ09B0219-0100