DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 37

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 14.41 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous
Figure 14.42 Sample Flowchart for Mode Transition during Reception .................................... 631
Figure 14.43 Block Diagram of CRC Operation Circuit ............................................................ 632
Figure 14.44 LSB-First Data Transmission ................................................................................ 635
Figure 14.45 MSB-First Data Transmission ............................................................................... 635
Figure 14.46 LSB-First Data Reception ..................................................................................... 636
Figure 14.47 MSB-First Data Reception .................................................................................... 637
Figure 14.48 LSB-First and MSB-First Transmit Data .............................................................. 638
Section 15 USB Function Module (USB)
Figure 15.1 Block Diagram of USB ........................................................................................... 640
Figure 15.2 Cable Connection Operation ................................................................................... 674
Figure 15.3 Cable Disconnection Operation............................................................................... 675
Figure 15.4 Suspend Operation .................................................................................................. 676
Figure 15.5 Resume Operation from Up-Stream ........................................................................ 677
Figure 15.6 Flow of Transition to and Canceling Software Standby Mode................................ 678
Figure 15.7 Timing of Transition to and Canceling Software Standby Mode ............................ 679
Figure 15.8 Remote-Wakeup...................................................................................................... 680
Figure 15.9 Transfer Stages in Control Transfer ........................................................................ 681
Figure 15.10 Setup Stage Operation ........................................................................................... 682
Figure 15.11 Data Stage (Control-In) Operation ........................................................................ 683
Figure 15.12 Data Stage (Control-Out) Operation...................................................................... 684
Figure 15.13 Status Stage (Control-In) Operation ...................................................................... 685
Figure 15.14 Status Stage (Control-Out) Operation ................................................................... 686
Figure 15.15 EP1 Bulk-Out Transfer Operation......................................................................... 687
Figure 15.16 EP2 Bulk-In Transfer Operation............................................................................ 688
Figure 15.17 Operation of EP3 Interrupt-In Transfer ................................................................. 690
Figure 15.18 Forcible Stall by Application................................................................................. 693
Figure 15.19 Automatic Stall by USB Function Module............................................................ 694
Figure 15.20 RDFN Bit Operation for EP1 ................................................................................ 695
Figure 15.21 PKTE Bit Operation for EP2................................................................................. 696
Figure 15.22 Example of Circuitry in Bus Power Mode ............................................................ 697
Figure 15.23 Example of Circuitry in Self Power Mode ............................................................ 698
Figure 15.24 TR Interrupt Flag Set Timing ................................................................................ 700
Section 16 I2C Bus Interface2 (IIC2)
Figure 16.1 Block Diagram of I
Figure 16.2 Connections to the External Circuit by the I/O Pins................................................ 705
Figure 16.3 I
Figure 16.4 I
2
2
Transmission) (Setting is Prohibited in SCI_5 and SCI_6) ................................... 631
C Bus Formats ...................................................................................................... 718
C Bus Timing........................................................................................................ 718
2
C Bus Interface2...................................................................... 704
Rev.1.00 Sep. 08, 2005 Page xxxv of xlviii