DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 423
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 423 of 1020
- Download datasheet (6Mb)
(3)
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF2DDR bit settings.
Note:
(4)
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF1DDR bit settings.
Note:
MCU
Operating Mode
On-chip ROM
disabled extended
mode
Modes other than
on-chip ROM
disabled extended
mode
MCU
Operating Mode
On-chip ROM
disabled extended
mode
Modes other than
on-chip ROM
disabled extended
mode
PF2/A18
PF1/A17
*
*
Valid in external extended mode (EXPE = 1)
Valid in external extended mode (EXPE = 1)
Module Name
Bus controller
Bus controller
I/O port
Module Name
Bus controller
Bus controller
I/O port
Pin Function
A18 output
A18 output*
PF2 output
PF2 input
(initial setting)
Pin Function
A17 output
A17 output*
PF1 output
PF1 input
(initial setting)
I/O Port
A18_OE
1
0
0
I/O Port
A17_OE
1
0
0
Rev.1.00 Sep. 08, 2005 Page 373 of 966
Setting
Setting
I/O Port
PF2DDR
1
0
I/O Port
PF1DDR
1
0
Section 9 I/O Ports
REJ09B0219-0100
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