DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 840

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
(1)
The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data,
one stop bit, and no parity.
When a transition to SCI boot mode is made, the boot program embedded in this LSI is initiated.
When the boot program is initiated, this LSI measures the low period of asynchronous serial
communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and
adjusts the bit rate of the SCI_4 to match that of the host.
When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit
adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1
byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The
bit rate may not be adjusted within the allowable range depending on the combination of the bit
rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the
host and the system clock frequency of this LSI must be as shown in table 20.6.
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
Rev.1.00 Sep. 08, 2005 Page 790 of 966
REJ09B0219-0100
Bit Rate of Host
9,600 bps
19,200 bps
Serial Interface Setting by Host
Start
bit
Figure 20.7 Automatic-Bit-Rate Adjustment Operation
D0
Measure low period (9 bits) (data is H'00)
D1
D2
D3
System Clock Frequency of This LSI
8 to 18 MHz
8 to 18 MHz
D4
D5
D6
D7
High period of
at least 1 bit
Stop bit