DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 336

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 DMA Controller (DMAC)
(3)
In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer
request is completed.
In figure 7.28, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer
mode.
Rev.1.00 Sep. 08, 2005 Page 286 of 966
REJ09B0219-0100
B
Address bus
RD
LHWR, LLWR
TEND
Block Transfer Mode
Bus
released
DMA read
cycle
Figure 7.28 Example of Transfer in Block Transfer Mode
DMA write
cycle
Block transfer
DMA read
cycle
DMA write
cycle
Bus
released
DMA read
cycle
DMA write
cycle
Last block transfer cycle
DMA read
cycle
DMA write
cycle
Bus
released

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