DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 484
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.9
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Rev.1.00 Sep. 08, 2005 Page 434 of 966
REJ09B0219-0100
Bit
7, 6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Timer Synchronous Register (TSYR)
R/W
7
0
Initial
Value
All 0
0
0
0
0
0
0
R/W
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYNC5
R/W
5
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timer Synchronization 5 to 0
These bits select whether operation is independent of
or synchronized with other channels.
When synchronous operation is selected, synchronous
presetting of multiple channels, and synchronous
clearing through counter clearing on another channel
are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operate independently (TCNT
1: TCNT_5 to TCNT_0 perform synchronous operation
SYNC4
presetting/clearing is unrelated to other channels)
(TCNT synchronous presetting/synchronous clearing
is possible)
R/W
4
0
SYNC3
R/W
3
0
SYNC2
R/W
2
0
SYNC1
R/W
1
0
SYNC0
R/W
0
0
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