DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 115

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch.
Bit
10
9
8
7 to 2
1
0
2. The initial value depends on the LSI initiation mode.
Bit Name
EXPE
RAME
DTCMD
Initial
Value
Undefined
Undefined
1
All 0
1
1
*
*
2
2
R/W
R
R/W
R/W
R/W
R/W
R/W
Descriptions
Reserved
This bit is fixed at 1 in on-chip ROM enabled mode, and
0 in on-chip ROM disabled mode. This bit cannot be
changed.
External Bus Mode Enable
Selects external bus mode. In external extended mode,
this bit is fixed 1 and cannot be changed. In single-chip
mode, the initial value of this bit is 0, and can be read
from or written to.
When writing 0 to this bit after reading EXPE = 1, an
external bus cycle should not be executed.
The external bus cycle may be carried out in parallel
with the internal bus cycle depending on the setting of
the write data buffer function.
0: External bus disabled
1: External bus enabled
RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is released. Do not write
0 during access to the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
DTC Mode Select
Selects DTC operating mode.
0: DTC is in full-address mode
1: DTC is in short address mode
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev.1.00 Sep. 08, 2005 Page 65 of 966
Section 3 MCU Operating Modes
REJ09B0219-0100

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