DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 247

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8.5
As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.6.4,
Wait Control. Wait cycles cannot be inserted in a burst cycle.
6.8.6
When the burst ROM space is read by the CPU, the RDNCR setting for the corresponding space is
invalid.
The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface.
6.8.7
In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus
interface.
For the burst ROM space, the burst access can be enabled only in read access by the CPU. In this
case, the setting of the corresponding CSXTn bit in CSACR is ignored and an extension cycle can
be inserted only before the full access cycle. Note that no extension cycle can be inserted before or
after the burst access cycles.
In accesses other than read accesses by the CPU, the burst ROM space is equivalent to the basic
bus interface space. Accordingly, extension cycles can be inserted before and after the burst access
cycles.
Wait Control
Read Strobe (RD) Timing
Extension of Chip Select (CS) Assertion Period
Rev.1.00 Sep. 08, 2005 Page 197 of 966
Section 6 Bus Controller (BSC)
REJ09B0219-0100