DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 757

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.1
ICCRA enables or disables I
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
I
2
Bit Name
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
C Bus Control Register A (ICCRA)
R/W
ICE
7
0
Initial
Value
0
0
0
0
0
0
0
0
RCVD
R/W
6
0
2
C bus interface, controls transmission or reception, and selects
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MST
R/W
5
0
Description
I
0: This module is halted
1: This bit is enabled for transfer operations (SCL and
Reception Disable
This bit enables or disables the next operation when
TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
When arbitration is lost in master mode, MST and
TRS are both reset by hardware, causing a transition
to slave receive mode. Modification of the TRS bit
should be made between transfer frames.
Operating modes are described below according to
MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
These bits are valid only in master mode. Make
setting according to the required transfer rate. For
details on the transfer rate, see Table 16.2.
2
C Bus Interface Enable
SDA pins are bus drive state)
TRS
R/W
4
0
CKS3
R/W
3
0
Rev.1.00 Sep. 08, 2005 Page 707 of 966
Section 16 I
CKS2
R/W
2
0
2
C Bus Interface2 (IIC2)
CKS1
R/W
1
0
REJ09B0219-0100
CKS0
R/W
0
0