DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 732

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 USB Function Module (USB)
(1)
Rev.1.00 Sep. 08, 2005 Page 682 of 966
REJ09B0219-0100
Setup Stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by
Receive 8-byte command
SETUP token reception
reception complete flag
2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status
(IFR0.SETUP TS = 1)
Set setup command
to be processed by
the application, and determines the subsequent processing (for example, data stage direction, etc.).
stage should be enabled here. When the transfer direction is control-in, this interrupt is not required
and should be disabled.
To data stage
data in EP0s
application?
Command
Yes
USB function
Figure 15.10 Setup Stage Operation
No
processing by
Interrupt request
this module
Automatic
Clear EP0o FIFO (FCLR.EP0oCLR = 1)
Clear EP0i FIFO (FCLR.EP0iCLR = 1)
To control-in
Write 1 to EP0s read complete bit
Determine data stage direction*
data stage
Read 8-byte data from EP0s
Decode command data
(TRG.EP0s RDFN = 1)
(IFR0.SETUP TS = 0)
Clear SETUP TS flag
Application
*
2
To control-out
data stage
1