DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 279

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI includes a 4-channel DMA controller (DMAC).
7.1
• Maximum of 4-G byte address space can be accessed
• Byte, word, or longword can be set as data transfer unit
• Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size
• DMAC activation methods are auto-request, on-chip module interrupt, and external request.
• Dual or single address mode can be selected as address mode
• Normal, repeat, or block transfer can be selected as transfer mode
Supports free-running mode in which total transfer size setting is not needed
Auto request:
On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected
External request:
Dual address mode: Both source and destination are specified by addresses
Single address mode: Either source or destination is specified by the DREQ signal and the
other is specified by address
Normal transfer mode:
Repeat transfer mode:
Block transfer mode:
Features
Section 7 DMA Controller (DMAC)
as an activation source
CPU activates (cycle stealing or burst access can be selected)
Low level or falling edge detection of the DREQ signal can be
selected. External request is available for all four channels.
In block transfer mode, low level detection is only available.
One byte, one word, or one longword data is transferred at a
single transfer request
One byte, one word, or one longword data is transferred at a
single transfer request
Repeat size of data is transferred and then a transfer address
returns to the transfer start address
Up to 65536 transfers (65,536 bytes/words/longwords) can be set
as repeat size
One block data is transferred at a single transfer request
Up to 65,536 bytes/words/longwords can be set as block size
Rev.1.00 Sep. 08, 2005 Page 229 of 966
Section 7 DMA Controller (DMAC)
REJ09B0219-0100