DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 578

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 8-Bit Timers (TMR)
12.8.5
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 12.6.
Table 12.6 Timer Output Priorities
12.8.6
TCNT may be incremented erroneously depending on when the internal clock is switched. Table
12.7 shows the relationship between the timing at which the internal clock is switched (by writing
to the bits CKS1 and CKS0) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal
clock pulse are always monitored. Table 12.7 assumes that the falling edge is selected. If the
signal levels of the clocks before and after switching change from high to low as shown in item 3,
the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and
TCNT is incremented. This is similar to when the rising edge is selected.
The erroneous increment of TCNT can also happen when switching between rising and falling
edges of the internal clock, and when switching between internal and external clocks.
Rev.1.00 Sep. 08, 2005 Page 528 of 966
REJ09B0219-0100
Output Setting
Toggle output
1-output
0-output
No change
Conflict between Compare Matches A and B
Switching of Internal Clocks and TCNT Operation
Priority
High
Low

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