DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 213

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(d) Address/data multiplexed I/O interface
The number of access cycles in data cycle of the address/data multiplexed I/O interface is the
same as that in the basic bus interface. The number of access cycles in address cycle can be
specified as two or three cycles by the ADDEX bit in MPXCR.
Table 6.6 lists the number of access cycles for each interface.
Table 6.6
(5)
The assert and negate timings of the strobe signals can be modified as well as number of access
cycles.
• Read strobe (RD) in the basic bus interface
• Chip select assertion period extension cycles in the basic bus interface
• Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers
Basic bus interface
Byte control SRAM interface
Burst ROM interface
Address/data multiplexed I/O
interface
[Legend]
Numbers: Number of access cycles
n:
m:
Strobe Assert/Negate Timings
Number of access cycles in the address/data multiplexed I/O interface
= number of address output cycles (2, 3) + number of data output cycles (2, 3)
Pin wait (0 to )
Number of burst accesses (0 to 63)
+ number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+number of external wait cycles by the WAIT pin]
Number of Access Cycles
=
=
=
=
=
=
= Tma
= Tma
[2,3]
[2,3]
Th
[0,1]
Th
[0,1]
Th
[0,1]
Th
[0,1]
Th
[0,1]
Th
[0,1]
+Th
+Th
[0,1]
[0,1]
+T1
+T1
+T1
+T1
+T1
+T1
+T1
+T1
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
+T2
+T2
+T2
+T2
+T2
+T2
+T2
+T2
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
+Tpw
+Tpw
+Tpw
+Tpw
[0 to 7]
[0 to 7]
[0 to 7]
[0 to 7]
+Ttw
+Ttw
+Ttw
+Ttw
[n]
[n]
[n]
[n]
+T3
+T3
+T3
+T3
[1]
[1]
[1]
[1]
Rev.1.00 Sep. 08, 2005 Page 163 of 966
+Tt
+Tt
+Tt
+Tt
+Tt
+Tt
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
+Tb
+Tb
[(1 to 8)
[(1 to 8)
Section 6 Bus Controller (BSC)
m]
m]
[(2 to 11 + n) + (1 to 8)
REJ09B0219-0100
[(2 to 3) + (1 to 8)
[3 to 12 + n]
[3 to 12 + n]
[5 to 15 + n]
[2 to 4]
[2 to 4]
[4 to 7]
m]
m]