DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 525

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.10.7 Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the write data.
Figure 10.49 shows the timing in this case.
10.10.8 Conflict between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 10.50 shows the timing in this case.
Figure 10.49 Conflict between Buffer Register Write and Compare Match
P
Address
Write
Compare match
signal
Buffer register
TGR
TGR write cycle
Buffer register
address
N
T
1
T
2
M
M
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.1.00 Sep. 08, 2005 Page 475 of 966
Data written to buffer register
REJ09B0219-0100