DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 142

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.3
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32,SP).
4.3.4
After reset release, MSTPCRA, MSTPCRB, and MSTPCRC are initialized and all modules except
the DMAC enter module stop mode. Consequently, on-chip peripheral module registers cannot be
read from or written to. Register reading and writing is enabled when module stop mode is exited.
Rev.7.00 Dec. 24, 2008 Page 86 of 698
REJ09B0074-0700
φ
RES, MRES
Internal
Address bus
Internal
read signal
Internal
write signal
Internal
data bus
(1) (3)
(2) (4)
(5)
(6)
Interrupts after Reset
State of On-Chip Peripheral Modules after Reset Release
: Reset exception handling vector address (for a power-on reset, (1) = H'000000, (3) = H'000002
: Start address (contents of reset exceptiion handling vector address)
: Start address ((5) = (2) (4))
: First program instruction
for a manual reset, (1) = H'000004, (3) = H'000006)
Figure 4.2 Reset Sequence (Modes 6 and 7)
(1)
(2)
Vector
fetch
High
(4)
(3)
Internal
processing
Prefetch of first program
instruction
(5)
(6)