DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 229

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
11
10
9
Bit Name
DTA1
DTA0
Initial Value R/W
0
0
0
R/W
R/W
R/W
Data Transfer Acknowledge
Enables or disables clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source
selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA
= 1, the internal interrupt source selected by the data
transfer factor setting does not issue an interrupt request
to the CPU.
When DTE = 1 and DTA = 0, the internal interrupt source
selected by the data transfer factor setting is not cleared
when a transfer is performed, and can issue an interrupt
request to the CPU in parallel. In this case, the interrupt
source should be cleared by the CPU transfer.
When DTE = 0, the internal interrupt source selected by
the data transfer factor setting issues an interrupt request
to the CPU regardless of the DTA bit setting.
The state of the DTME bit does not affect the above
operations.
Enables or disables clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
channel 1 data transfer factor setting.
0: Clearing of selected internal interrupt source at time of
1: Clearing of selected internal interrupt source at time of
Reserved
Although this bit is readable/writable, only 0 should be
written to.
Data Transfer Acknowledge 0
Enables or disables clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
channel 0 data transfer factor setting.
0: Clearing of selected internal interrupt source at time of
1: Clearing of selected internal interrupt source at time of
Description
Data transfer acknowledge 1
DMA transfer is disabled
DMA transfer is enabled
DMA transfer is disabled
DMA transfer is enabled
Rev.7.00 Dec. 24, 2008 Page 173 of 698
REJ09B0074-0700

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