DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 318

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.11.1
PFDDR specifies input or output for the pins of the port F.
Since PFDDR is a write-only register, the bit manipulation instructions must not be used to write
PFDDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Notes: 1. The initial value becomes 1 in modes 4 to 6 and 0 in mode 7.
Rev.7.00 Dec. 24, 2008 Page 262 of 698
REJ09B0074-0700
Bit
7
6
5
4
3
2
1
0
Bit Name
PF7DDR
PF6DDR*
PF5DDR*
PF4DDR*
PF3DDR
PF2DDR*
PF1DDR*
PF0DDR
2. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.
Port F Data Direction Register (PFDDR)
This bit cannot be modified.
2
2
2
2
2
Initial Value
1/0*
0
0
0
0
0
0
0
1
R/W
W
W
W
W
W
W
W
W
Description
(H8S/2218 Group)
Modes 4 to 6:
Pin PF7 functions as the φ output pin when the PF7DDR
bit is set to 1, and as an input port when the bit is cleared
to 0. Pins PF6 to PF3 are automatically designated as bus
control output pins. Pins PF2 to PF0 are made bus control
input/output pins by bus controller settings. Otherwise,
setting a PFDDR bit to 1 makes the corresponding pin an
output port, while clearing the bit to 0 makes the pin an
input port.
Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F
pin PF6 to PF0 an output port, or in the case of pin PF7,
the φ output pin. Clearing the bit to 0 makes the pin an
input port.
(H8S/2212 Group)
Setting a PFDDR bit to 1 makes the corresponding port F
pin PF6 to PF0 an output port, or in the case of pin PF7,
the φ output pin. Clearing the bit to 0 makes the pin an
input port.