DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 525

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
5
4
3
2
Bit Name
UCKS3
UCKS2
UCKS1
UCKS0
Initial Value R/W
0
R/W
Description
USB Operation Clock Select 3 to 0
These bits control the on-chip PLL, which generates
the USB operation clock (48 MHz). When UCKS3 to
UCKS0 are 0000, the PLL circuit stops and thus the
USB operation clock must be selected according to
the clock source.
The on-chip PLL circuit starts operating after the USB
module stop 2 bit has been cancelled. In addition, the
USB operation clock is supplied to the UDC core after
the USB operating clock stabilization time has been
passed. The completion timing of the USB operating
clock stabilization time can be detected by the
CK48READY flag in UIFR3.
UCKS0 to UCKS3 muse be written while the USB
module stop 2 bit (MSTPB0) is 1.
0000: USB operation clock stops (PLL stops)
0001: Reserved
001×: Reserved
010×: Reserved
0110: Uses a clock (48 MHz) generated by doubling
0111: Uses a clock (48 MHz) generated by tripling the
1×××: Reserved
The USB operating clock stabilization time is 2 ms.
Legend:
×: Don't care
the 24-MHz main oscillation by the PLL.
16-MHz main oscillation by the PLL.
Rev.7.00 Dec. 24, 2008 Page 469 of 698
REJ09B0074-0700

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