DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 669

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.1.2
TCSR_1 controls the operation in power-down mode transition.
Bit
7 to 5 ⎯
4
3 to 0 —
Bit Name
PSS
Timer Control/Status Register (TCSR_1)
All 0
0
All 0
Initial Value
R/W
R/W
Description
Reserved
The write value should always be 0.
Prescaler Select
0: When the SLEEP instruction is executed in high-
1: When the SLEEP instruction is executed in high-
Write:
TCSR_1 must be written to by a word transfer
instruction. The upper byte of the written word must
contain H′A5 and the lower byte must contain the
write data. (When the PSS bit is set to 1, the upper
byte of the written word must contain H'A510.)
Read:
TCSR_1 is read by the same procedure as for the
general registers.
Reserved
The write value should always be 0.
TCSR_1 differs from other registers in being more
speed mode or medium-speed mode, operation
shifts to sleep mode or software standby mode.
speed mode or medium-speed mode, operation
shifts to sleep mode, watch mode, or subactive
mode.
When the SLEEP instruction is executed in
subactive mode, operation shifts to subsleep
mode, watch mode, or high-speed mode
difficult to write to. The procedures for writing to
and reading this register are given below.
Rev.7.00 Dec. 24, 2008 Page 613 of 698
REJ09B0074-0700

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