DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 492

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.7.9
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1
in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure
12.34 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is
cleared to 0, and the CKE0 bit is controlled.
Rev.7.00 Dec. 24, 2008 Page 436 of 698
REJ09B0074-0700
CKE0
SCK
Clock Output Control
No
Figure 12.33 Example of Reception Processing Flow
No
Figure 12.34 Timing for Fixing Clock Output Level
Specified pulse width
RDRF flag in SSR to 0
Read RDR and clear
All data received?
Clear RE bit to 0
ORER = 0 and
Start reception
Initialization
RDRF = 1?
PER = 0
Start
Yes
Yes
Yes
No
Specified pulse width
Error processing

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