DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 538

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.17 USB Interrupt Flag Register 1 (UIFR1)
UIFR1 is an interrupt flag register indicating the EP1 and EP2 status. If the corresponding bit is set
to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. EP1TR flags can
be cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
Consequently, to clear a flag, write 0 to the corresponding bit and 1 to all the other bits. (For
example, write H'FD to clear bit 1.) The bit-clear instruction is a read/modify/write instruction, so
if a new flag is set between the read and write operations, there is a danger that it may be cleared
erroneously. Therefore, do not use the bit-clear instruction to clear bits in this interrupt flag
resister. However, EP1EMPTY, EP2READY, and EP1ALLEMPTYs are status bits to indicate the
EP1, EP2, and FIFO state respectively, and cannot be cleared.
Note:* The write value should always be 0 to clear this flag.
Rev.7.00 Dec. 24, 2008 Page 482 of 698
REJ09B0074-0700
Bit
7 to 4 —
3
2
1
0
Bit Name
EP1ALL
EMPTYs
EP2READY 0
EP1TR
EP1EMPTY 1
Initial Value R/W
All 0
1
0
R
R
R
R/(W)* EP1 Transfer Request
R
Description
Reserved
These bits are always read as 0 and cannot be
modified.
EP1 FIFO All Empty Status
EP1 FIFO has a dual-FIFO configuration. This bit is set
to 1 if there is no valid data in both FIFOs. This
corresponds to the negative-electrode signal for the
EP1DE bit in UDSR.
An interrupt cannot be required by EP1ALLEMPTY.
EP2 Data Ready
EP2 FIFO has a dual-FIFO configuration. This bit is set
to 1 if there is valid data at least in either of FIFOs.
This bit is cleared to 0 if there is no valid data in both
FIFOs. This bit is a status bit and cannot be cleared.
The corresponding interrupt output is EXIRQ0 or
EXIRQ1.
Set to 1 if there is no valid data in both FIFOs when an
IN token is sent from the host to EP1. The
corresponding interrupt output is EXIRQ0 or EXIRQ1.
EP1 FIFO Empty
EP1 FIFO has a dual-FIFO configuration. This bit is set
to 1 if there is no valid data at least in either of FIFOs.
This bit is cleared to 0 if there is valid data in both
FIFOs. This bit is a status bit and cannot be cleared.
The corresponding interrupt output is EXIRQ0 or
EXIRQ1.